5 Verilog Static Analysis Tools, Linters, And Code Formatters

The Best Verilog Static Analysis Tools (Linters/Formatters)

We rank 5 Verilog linters, code analyzers, formatters, and more. Find and compare tools like Verilator, svls, vscode-verilog-hdl-support, and more. Please rate and review tools that you've used. This helps others find the best tools for their projects.

5 Verilog Tools

Sort by:

Verilator

A tool which converts Verilog to a cycle-accurate behavioral model in C++ or SystemC. Performs lint code-quality checks.

verilog

Maintained
Verilog
cli
linter
86% upvoted

svls

A Language Server Protocol implementation for Verilog and SystemVerilog, including lint capabilities.

verilog

Maintained
Verilog
cli
linter
100% upvoted

vscode-verilog-hdl-support

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code. Provides syntax highlighting and Linting support from Icarus Verilog, Vivado Logical Simulation, Modelsim and Verilator

verilog

Maintained
Verilog
ide-plugin
linter
100% upvoted

Icarus Verilog

A Verilog simulation and synthesis tool that operates by compiling source code written in IEEE-1364 Verilog into some target format

verilog

Maintained
Verilog
cli
linter
100% upvoted

verible-linter-action

Automatic SystemVerilog linting in github actions with the help of Verible Used to lint Verilog and SystemVerilog source files and comment erroneous lines of code in Pull Requests automatically.