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A tool which converts Verilog to a cycle-accurate behavioral model in C++ or SystemC. Performs lint code-quality checks.

Tutorials / Guides

  • Verilator screenshot
  • Verilator screenshot

2 Alternatives to Verilator

Icarus Verilog

A Verilog simulation and synthesis tool that operates by compiling source code written in IEEE-1364 Verilog into some target format


A Language Server Protocol implementation for Verilog and SystemVerilog, including lint capabilities.

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