Verilator logo

Verilator

MaintainedMaintained

A tool which converts Verilog to a cycle-accurate behavioral model in C++ or SystemC. Performs lint code-quality checks.

Tutorials / Guides

  • Verilator screenshot
  • Verilator screenshot

2 Alternatives for Verilator

Icarus Verilog

A Verilog simulation and synthesis tool that operates by compiling source code written in IEEE-1364 Verilog into some target format

svls

A Language Server Protocol implementation for Verilog and SystemVerilog, including lint capabilities.

Our Sponsors

This website is completely open source. To fund our work, we fully rely on sponsors. Thanks to them, we can keep the site free for everybody. Please check out their offers below.

  • Bearer
  • BugProve
  • CodeScene
  • semgrep
  • Offensive 360